1. Field of the Invention
The present invention relates generally to a method for forming patterns, and more specifically to a method for forming patterns that can be applied to layouts having a sacrificial pattern with a dimension larger than the exposure limit, wherein the method can be paired with a self-aligned via process to prevent the sacrificial pattern from being formed on the wafer.
2. Description of the Prior Art
In semiconductor fabrication processes, lithography processes are important steps to transfer integrated circuit layouts to semiconductor wafers. A wafer manufacturing company designs a mask layout according to an integrated circuit layout and then fabricates a mask having the designed mask layout. By way of lithography processes, the pattern on the mask (i.e. the mask pattern) is transferred to a photoresist layer on the surface of a semiconductor wafer with a specific scale.
As the complexity and integration of integrated circuits continues to progress, the size of each segment of a mask pattern is designed to be smaller. The exposure limit of every segment fabricated by exposure is limited to the resolution limit of the optical exposure tool used during the transfer step of the mask pattern, however. One problem that easily arises during the exposure of a mask pattern with high-density arranged segments to form a pattern on a photoresist is the optical proximity effect. Resolution losses occur because of overexposure or underexposure, which causes deviations in the original pattern on the photoresist. Many methods have been used to improve deviation caused by the optical proximity effect in order to improve the quality of the transferred pattern. The most popular method is the optical proximity correction (OPC). There is a variety of commercial optical proximity correction software that can theoretically correct the mask pattern in order to acquire more accurate patterns on a wafer.